In the ever-continuing effort to improve the performance of metal-oxide-silicon (MOS) devices it has been discovered that the current leakage properties of a short p-channel MOS (PMOS) transistor may be improved by introducing a deep arsenic implant underneath the shallow boron channel implant. See, for example, S. Chiang, et al. "Optimization of Sub-micron p-Channel FET Structure," IEEE International Electronic Devices Meeting Papers, Vol. 24.6 1983, pp. 534-537. The use of a deep, n.sup.- channel implant under p-channel devices does not cause a process sequence problem if all of the devices on the integrated circuit under construction are PMOS, however, if this technique were used to enhance the characteristics of p-channel devices in CMOS, one skilled in the art would expect that a mask step would be necessary to prevent the deep, buried n.sup.- channel implant from appearing under the n-channel devices present. The expectation is that an n.sup.- channel implant under an NMOS device would create punchthrough problems.
It would be desirable to discover a process by which the deep, buried n.sup.- channel implant of PMOS devices could be applied to CMOS integrated circuits without the addition of an extra mask step.